1. Field of the Invention
The present invention relates to a MOS Trnsistor of semiconductor device and method of manufacturing the same and, in particular, to a MOS transistor of semiconductor device and method of manufacturing the same which can reduce asymmetry of drain current due to bias, facilitate shallow junction and reduce the area to a minimum by forming a source/drain in self-alignment method and diffusion method.
2. Disclosure Statement
In general, a MOS transistor consists of a gate, source and drain. A manufacturing process of the transistor is described below with reference to FIG. 1.
An active region and field region are defined by forming a field oxide film 2 in a semiconductor substrate 1 through a device separation mask process. A gate electrode 8 is formed on the semiconductor substrate 1 in the active region, and a gate oxide film 7 is formed between the semiconductor substrate 1 and gate electrode 8. A source/drain 4 of LDD structure formed by performing an ion implantation process in duplicate and spacer oxide films 6 are formed on both sides of the gate electrode 8 to complete the transistor. An interlayer insulation film 3 is formed on the semiconductor substrate 1 including the transistor for electric insulation between devices and protection of devices, and a metal electrode 5 which is connected to the source/drain 4 is formed through a metal contact process.
In case of NMOS device, a p-well is formed in the semiconductor substrate 1 through p-type impurity implantation process, and in case of PMOS device, a n-well is formed in the semiconductor substrate 1 through n-type impurity implantation process. The gate electrode 8 is formed with polycrystal silicon and the interlayer insulation film 3 is formed with BPSG which has superior flow characteristics. The source/drain 4 are formed through an ion implantation process and heat treatment process after formation of the field oxide film 2 and gate electrode 8.
As described above, since the source/drain are formed by heat treatment after ion implantation in the conventional device technology, an angle of ion implantation at the time of ion implantation and the bias of the source/drain 4 at the time of operation of device vary to inevitably cause asymmetry to degrade the performance of device. This phenomenon becomes further profound as the device is highly integrated. Furthermore, as the device is highly integrated, the junvyion depth of source/drain 4 must be decreased to the same ratio, however, it is very difficult to achieve that in the conventional device technology. In particular, in manufacturing PMOS device, the source/drain 4 junction is mainly obtained through heat treatment after implantation of Borous(B) ion, however, it is very difficult to from the shallow junction since the diffusion coefficient of Boron(B) is large. Therefore, various methods are used to achieve that, the typical one among them is to use rapid theamal annealing(RTA) method to form the shallow junction after ion implantation into the source/drain 4 according to a conventional method. However, this method has various problems in manufacturing an integrated circuit due to poor uniformity of process and leakage current.